1. Introduction The HS6200 is a single chip 2.4GHz transceiver with an embedded baseband protocol engine, suitable for ultralow power wireless applications. The HS6200 is designed for operation in the world wide ISM frequency band at 2.400 - 2.4835GHz. To design a radio system with the HS6200, you simply need an MCU (microcontroller) and a few external passive components. You can operate and configure the HS6200 through a Serial Peripheral Interface (SPI). The register map, which is accessible through the SPI, contains all configuration registers in the HS6200 and is accessible in all operation modes of the chip. The embedded baseband protocol engine is based on packet communication and supports various modes from manual operation to advanced autonomous protocol operation. Internal FIFOs ensure a smooth data flow between the radio front end and the system’s MCU. Protocol engine reduces system cost by handling all the high speed link layer operations. The radio front end uses GFSK modulation. It has user configurable parameters like frequency channel, output power and air data rate. HS6200 supports an air data rate of 500kbps, 1Mbps and 2Mbps. The high air data ratescombined with two power saving modes make the HS6200 very suitable for ultralow power designs. The addition of internal filtering to HS6200 has improved the margins for meeting RF regulatory standards. Internal voltage regulators ensure a high Power Supply Rejection Ratio (PSRR) and a wide power supply range.
1.1 Features Features of the HS6200 include: 1）Radio: 。Worldwide 2.4GHz ISM band operation 。126 RF channels 。Common RX and TX interface 。GFSK modulation 。500kbps, 1 and 2Mbps air data rate 。1MHz non-overlapping channel spacing at 1Mbps 。2MHz non-overlapping channel spacing at 2Mbps 2）Transmitter: 。Programmable output power: 0, -6, -12 or -16dBm。 (8dBm@3.3V) 。18.5mA at 0dBm output power 3）Receiver: 。Fast AGC for improved dynamic range 。Integrated channel filters 。19.5mA at 2Mbps 。-85dBm sensitivity at 2Mbps 。-88dBm sensitivity at 1Mbps 。-90dBm sensitivity at 500kbps 4）RF Synthesizer: 。Fully integrated synthesizer 。No external loop filer, VCO varactor diode or resonator 。Accepts low cost ±60ppm 16MHz crystal 5）Protocol engine: 。1 to 32 bytes dynamic payload length 。Automatic packet handling 。Auto packet transaction handling 。6 data pipe for 1:6 star networks 6）Power Management: 。Integrated voltage regulator 。1.8 to 3.6V supply range 。Idle modes with fast start-up times for advanced power management 。30µA Standby-I mode,4uA power down mode 。Max 2ms start-up from power down mode 。Max 210us start-up from standby-I mode 7）Host Interface: 。4-pin hardware SPI 。Max 10Mbps 。3 separate 32 bytes TX and RX FIFOs 。5V tolerant IO 8）Support 20-pin 4x4mm QFN, SOP16/SSOP16 and COB package
Figure1.1HS6200 block diagram
Figure2.1HS6200 pin assignment (top view) for the QFN20 4x4 package
Figure2.2HS6200 pin assignment (top view) for the SOP16 package